The invention lies in the electrical arts. Specifically, the present invention relates to a power switch of the type disclosed in the commonly assigned U.S. Pat. No. 5,821,618 (see European patent application EP 0 696 818). The reference describes a semiconductor chip on a leadframe. The semiconductor chip has at least one gate terminal, one first terminal for an active potential and one second terminal for an inactive potential. The leadframe is connected to the second terminal.
Power switchs, in particular power transistors, which operate on the basis of fast switching processes cause a high level of electromagnetic interference emission. In order to comply with the maximum interference emission limits specified in the relevant EMC Standards (for example, EN50081 11/2), a quite considerable filter complexity is therefore required in most practical circuits.
With regard to conducted interference, a distinction is drawn between differential-mode and common-mode interference, with common-mode interference being caused by the interference currents coupled into the ground or frame path. The origin of common-mode interference will be explained in the following text with reference to a single-ended converter.
If the power switch is a power MOS transistor, then high voltages occur at the drain terminal of the power transistor during switching operation, that is to say the voltage profile has a steep gradient dU/dt. Since, in all power transistors according to the prior art, the rear side of the chip facing the heatsink forms the drain terminal and is connected to the leadframe, this results, when the component is mounted on a heatsink, in a considerable coupling capacitance Ck between the drain and the heatsink. (The leadframe, of course, is the metal base on which the actual semiconductor chip is mounted.) The heatsink itself is generally connected to frame potential directly or via a coupling capacitance, which is not insignificant owing to its physical extent. An interference current which is proportional to the rate of voltage change, that is to say, Iintxcx9cCkxc2x7dU/dt, is now coupled into the frame line via the coupling capacitance Ck.
That situation is illustrated in FIG. 2 (see U.S. Pat. No. 4,961,107). A power transistor 6 according to the prior art has its drain terminal connected directly to the leadframe 2. A load 4 is connected in the drain path of the power transistor 6. A capacitance CK is formed by the leadframe 2 and the heatsink 1 with insulation 9 between the two, via which capacitance CK the power switch is capacitively coupled to frame and via which an interference current Iint is coupled into the frame line. Owing to the large area of the leadframe, the capacitance CK assumes a large value, as a result of which the current Iint coupled into the frame line is also large.
After the coupling process, these common-mode current elements can be removed from the frame line only with great difficulty; for example, in mains-powered appliances, the size of the Y-capacitors required to filter out the common-mode interference is severely limited by considerations relating to the maximum dissipation current, thus leading to increased complexity for current-compensated suppression inductors.
In order to suppress the occurrence of common-mode interference, the prior art uses a conductive shield between the transistor and the heatsink, and the shield is connected with low inductance to the intermediate circuit potential. The interference current path to frame is thus interrupted.
However, the disadvantages of this suppression method are that the assembly complexity is considerably increased and the thermal resistance between the transistor and the heatsink is increased.
It is accordingly an object of the invention to provide an EMC-optimized power switch, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which suppresses common-mode interference, and at the same time reduces the circuit complexity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a power switch, comprising:
a leadframe;
a semiconductor chip on the leadframe; and
a transistor formed on the semiconductor chip, the transistor having a drain forming a first terminal for an active potential and having a source forming a second terminal connected to the leadframe for an inactive potential.
In other words, the basic premise of the invention is that the leadframe of the power switch is connected to that side of the chip which is at the xe2x80x9cinactive potential.xe2x80x9d
The term xe2x80x9cinactive potentialxe2x80x9d as used herein means the potential which is present on the side of the power switch facing away from the load. The xe2x80x9cactive potential,xe2x80x9d on the other hand, is that potential which is present on the load side of the power switch.
In the power switch according to the invention, which comprises a semiconductor chip on a leadframe, in which case the semiconductor chip has at least one first terminal for an active potential and one second terminal for an inactive potential. The leadframe is connected to the second terminal. In the embodiment in which the chip carries a transistor switch, the first terminal is the drain, and the second terminal is the source, of the transistor. The chip can in this case be completely insulated from the leadframe, and the terminal between the source and the leadframe is produced by a wire link.
In accordance with an added feature of the invention, the semiconductor chip is mounted on the leadframe via a source of the transistor. Since the chip is mounted on the leadframe via the source terminal, the drain terminal is located on the exposed surface of the chip.
In accordance with an additional feature of the invention, the semiconductor chip has an exposed surface and trenches formed therein, and wherein the transistor has a gate terminal connected to the exposed surface of the semiconductor chip via the trenches in the semiconductor chip. Since, in this embodiment, the gate (which is arranged adjacent to the source) is likewise located on the side of the leadframe, the gate terminal is connected to the exposed surface of the chip via the trenches in the chip. It is thus accessible and can be wired up.
With the above and other objects in view there is provided, in accordance with the invention, a power switch which is configured with a diode. Similarly to the above embodiment, the device has a semiconductor chip on a leadframe. The diode has a cathode forming the first terminal for an active potential and an anode for the inactive potential. The leadframe is connected to the anode.
Such an EMC-optimized switch has the following advantages: firstly, common-mode interference elements are suppressed without any additional shield. Secondly, the thermal resistance is not increased by shield insulation. Finally, owing to the lack of source bonding wires, the transistors have an extremely low source inductance. This effectively reduces parasitic oscillations in the area of the switching flanksxe2x80x94particularly when a plurality of transistors are connected in parallel. These oscillations are evident as maxima in the interference spectrum, whose attenuation in transistors according to the prior art (common drain) involves considerably increased complexity (auxiliary source terminal, resistors on the gate and source sides for the gate driver, etc.), which is obviated with the transistor according to the invention.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an EMC-optimized power switch, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in terminal with the accompanying drawings.